1. Field of the Invention
The present invention relates to a computer aided method for power-source wiring design of semiconductor integrated circuits, and also relates to a computer aided apparatus therefor.
2. Description of the Prior Art
In layout design of large scale integrated circuits, computer aided layout systems are widely used. In a conventional layout system, the layout procedure includes deciding a rough layout on a chip by a floor plan, and deciding channel of special wires such as a power source line and clocks, then deciding details of arrangement of general cells in accordance with the floor plan, so as to complete wiring.
Conventionally, with respect to the general wiring, various automatic wiring algorithms have been proposed and utilized. However, with respect to the power source wiring, since electric currents flowing in respective portions are different from one another, the widths of respective wires should be changed in accordance with respective amounts of the currents. Accordingly, it is very difficult to automatically design the wiring, and thus there are few methods of the power source wiring. Among them, is a a method of power source wiring in which the width of each wire is changed in accordance with an amount of an electric current, proposed by Ulrich Lauther in a report entitled "CHANNEL ROUTING IN A CELL ENVIRONMENT" in (VLSI 85: Proc. IFIP TC10/WG10.5 INT'L CONF. on VLSI, pp. 389-399, Tokyo JAPAN, Aug. 1985).
According to the report, the method is used under the condition of metal one-layer wiring, and has a special tree structure of power-source.ground wiring, so as not to generate shorts. Moreover, the width of each wire is decided by estimating each amount of currents flowing in the power-source.ground wires.
For gate arrays and the like, another method of power-source.ground wiring has been adopted. The method of power-source.ground wiring widely used for gate arrays is called macro cell, in which elements having independent functions are arranged in rows or lines, and power source lines and ground lines are provided over the arrangement. Moreover, in some standard cell system, the power source lines and the ground lines are projected from sides of each macro cell, so that the power-source.ground wiring over the entire body of a standard cell can be constructed only by arranging respective macro cells such that each adjacent pair of the cells are in contact with each other through their sides.
In production of semiconductor integrated circuits in such a gate array or standard cell system, typically, two or more metal wiring layers are used. Accordingly, there are many cases in which uses of the wiring layers are divided. For example, the vertical power-source.ground wiring is provided in the first wiring layer and the horizontal is provided in the second and the like.
In designing integrated circuits of the gate array or standard cell system, since a space capable of use for wiring is very small, it is preferred that the width of the power-source.ground wiring be reduced. However, when the width of wiring becomes too small, electromigration is likely to be caused. Accordingly, the current amount must be restricted so that it becomes difficult to provide the necessary amount of current. Further, the electric potential of the power source or ground is likely be changed by the wiring resistance. To avoid these problems, there is known a method in which compensation of the power source is carried out by wiring provided in another layer oriented vertically to the original power-source.ground wiring. However, the compensation of the power source requires a considerably wide space, so that it is very difficult to automatically design a suitable wiring structure while assuring satisfactory characteristics and reliability. Accordingly, to actually carry out the wiring method, the design must be directly dealt with by a designer with a graphic editor and the like.
Since the power consumption of a semiconductor integrated circuit and the amount of a current flowing in the power source lines change in respective regions in a chip, if it is possible to compensate the power source in accordance with distribution of the power consumption in the chip, the space can be more effectively used for the wiring.
With respect to a method for exactly estimating information concerning the power consumption from load capacitance, respective sizes of transistors and frequency of switching, the principles are partly introduced in "Switching Probability of Logic Circuits" reported by Hori et al. in the semiconductor material section at the all Japan meeting 2-67 of Electronic Communication Meeting '60 or in page 340 of "Introduction to VLSI systems" Addison-Wesley 1980 written by Carver Mead et al. However, to unify these principles as a CAD system so that designers can use the system with ease, various technological difficulties still remain.
Therefore, such an estimation means has not been practically used for the design, in almost all cases, the width of power-source.ground wiring has been manually decided by calculating the power consumption of respective portions in a logic circuit. Moreover, in the design of semiconductor circuits by the gate array or standard cell system, automatic layout is frequently utilized. Therefore, the mutual relation between the manually-decided portions and the automatic layout portions in a logic circuit is likely to be unclear, so that it becomes difficult to manually estimate power consumption of the respective automatic layout portions. As a result, failure of the design is likely. To avoid such failure, the power-source compensation is provided as large as possible in number after wiring, and the effect is not necessarily obtained quantitatively.
Moreover, among methods of optimizing semiconductor circuits, there is known a method in which a non-linear optimization technique is used, as reported in Chapter 6 of "Computer-Aided Network Design", McGraw-Hill, USA (1972) written by Donald A. Calahan. However, the object of these method does not relate to the wiring of power source lines and ground lines, but focuses on optimizing signals to be processed in a circuit. In this case, the compensation technique method by changing connection structure or addition of power source lines is not considered. Accordingly, this method is also insufficient as a method of actually optimizing the power source lines.
As stated above, in the layout design of ASIC by conventional methods of designing power source wiring, it is very difficult to provide the most suitable and effective wiring on a chip, in view of maldistribution of the power consumption thereon, without using unnecessary power source lines and ground lines, and it is also difficult to decide power-source.ground channels having satisfactory electric characteristics and life span.
To solve these problems, it is necessary to develop a method for calculating the power consumption and the maximum current amount in respective regions of a chip with high accuracy, a method and an apparatus for deciding a necessary power-source.ground wiring mode from the power consumption and current amounts of the respective regions, and automatically realizing the mode in a layout, and a method and apparatus for displaying the layout pattern on an interactive apparatus so that designers can well recognize it.